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1 mx25l1608e datasheet p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
2 contents features .................................................................................................................................................................. 5 general description ......................................................................................................................................... 6 pin configurations ............................................................................................................................................. 7 pin description ...................................................................................................................................................... 7 block diagram ....................................................................................................................................................... 8 memory organization ......................................................................................................................................... 9 table 1. memory organization ............................................................................................................................ 9 device operation ................................................................................................................................................ 10 figure 1. serial modes supported ....................................................................................................... 10 data protection .................................................................................................................................................. 11 table 2. protected area sizes ............................................................................................................................ 12 hold features ..................................................................................................................................................... 13 figure 2. hold condition operation ........................................................................................................ 13 command description ....................................................................................................................................... 14 table 4. command definition ..................................................................................................................... 14 (1) write enable (wren) ................................................................................................................................... 15 (2) write disable (wrdi) .................................................................................................................................... 15 (3) read status register (rdsr) ...................................................................................................................... 15 (4) write status register (wrsr) ...................................................................................................................... 16 table 5. protection modes .................................................................................................................................. 17 (5) read data bytes (read) ............................................................................................................................. 18 (6) read data bytes at higher speed (fast_read) ....................................................................................... 18 (7) dual output mode (dread) ......................................................................................................................... 18 (8) sector erase (se) ......................................................................................................................................... 18 (9) block erase (be) ........................................................................................................................................... 19 (10) chip erase (ce) .......................................................................................................................................... 19 (11) page program (pp) ..................................................................................................................................... 19 (12) deep power-down (dp) .............................................................................................................................. 20 (13) release from deep power-down (rdp), read electronic signature (res) ............................................. 20 (14) read identifcation (rdid) .......................................................................................................................... 21 (15) read electronic manufacturer id & device id (rems) .............................................................................. 21 table 6. id definitions ................................................................................................................................. 21 (16) enter secured area (ensa) ........................................................................................................ 21 (17) exit secured area (exsa) ........................................................................................................... 21 (18) read security register (rdscur) ............................................................................................................ 22 table 7. security register definition ................................................................................................... 22 (19) write security register (wrscur) ............................................................................................................ 22 power-on state ................................................................................................................................................... 23 p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
3 electrical specifications .............................................................................................................................. 24 absolute maximum ratings ..................................................................................................................... 24 figure 3.maximum negative overshoot waveform ........................................................................................... 24 capacitance ta = 25 c, f = 1.0 mhz ............................................................................................................. 24 figure 4. maximum positive overshoot waveform ............................................................................................ 24 figure 5. input test waveforms and measurement level .............................................................. 25 figure 6. output loading ........................................................................................................................... 25 table 8. dc characteristics ...................................................................................................................... 26 table 9. ac characteristics ...................................................................................................................... 27 timing analysis ........................................................................................................................................................ 28 figure 7. serial input timing .............................................................................................................................. 28 figure 8. output timing ...................................................................................................................................... 28 figure 9. hold timing ......................................................................................................................................... 29 figure 10. wp# disable setup and hold timing during wrsr when srwd=1 ............................................... 29 figure 11. write enable (wren) sequence (command 06) ............................................................................. 30 figure 12. write disable (wrdi) sequence (command 04) .............................................................................. 30 figure 13. read status register (rdsr) sequence (command 05) ................................................................ 31 figure 14. write status register (wrsr) sequence (command 01) ............................................................... 31 figure 15. read data bytes (read) sequence (command 03) ...................................................................... 31 figure 16. read at higher speed (fast_read) sequence (command 0b) ................................................... 32 figure 17. dual output read mode sequence (command 3b) ......................................................................... 33 figure 18. sector erase (se) sequence (command 20) .................................................................................. 33 figure 19. block erase (be) sequence (command 52 or d8) .......................................................................... 33 figure 20. chip erase (ce) sequence (command 60 or c7) ........................................................................... 34 figure 21. page program (pp) sequence (command 02) ................................................................................ 34 figure 22. deep power-down (dp) sequence (command b9) ......................................................................... 35 figure 23. release from deep power-down (rdp) sequence (command ab) ............................................... 35 figure 24. release from deep power-down and read electronic signature (res) sequence (command ab) 35 )ljxuh5hdg,ghqwlfdwlrq5','6htxhqfh&rppdqg) ...................................................................... 36 figure 26. read electronic manufacturer & device id (rems) sequence (command 90) .............................. 36 )ljxuh3urjudp(udvhrzzlwuhdgduudgdwd ......................................................................................... 37 figure 28. power-up timing ............................................................................................................................... 38 table 10. power-up timing ............................................................................................................................... 38 operating conditions ....................................................................................................................................... 39 figure 29. ac timing at device power-up ......................................................................................................... 39 figure 30. power-down sequence .................................................................................................................... 40 erase and programming performance .................................................................................................... 41 data retention .................................................................................................................................................... 41 latch-up characteristics .............................................................................................................................. 41 p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
4 ordering information ...................................................................................................................................... 42 part name description ..................................................................................................................................... 43 package information ........................................................................................................................................ 44 revision history ................................................................................................................................................. 45 p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
5 16m-bit [x 1 / x 2] cmos serial flash features general ? single power supply operation - 2.7 to 3.6 volt for read, erase, and program operations ? serial peripheral interface compatible -- mode 0 and mode 3 ? 16,777,216 x 1 bit structure or 8,388,608 x 2 bits (dual output mode) structure ? 512 equal sectors with 4k byte each - any sector can be erased individually ? 32 equal blocks with 64k byte each - any block can be erased individually ? program capability - byte base - page base (256 bytes) ? latch-up protected to 100ma from -1v to vcc +1v performance ? high performance - fast access time: 86mhz serial clock - serial clock of dual output mode : 80mhz - fast program time: 0.6ms(typ.) and 3ms(max.)/page - byte program time: 9us (typ.) - fast erase time: 40ms(typ.) /sector ; 0.4s(typ.) /block ? low power consumption - low active read current: 25ma(max.) at 86mhz - low active programming current: 15ma (typ.) - low active sector erase current: 9ma (typ.) - standby current: 15ua (typ.) - deep power-down mode 2ua (typ.) ? typical 100,000 erase/program cycles ? 20 years of data retention software features ? input data format - 1-byte command code ? advanced security features - block lock protection the bp3~bp0 status bit defnes the size of the area to be software protection against program and erase instruc - tions - additional 512 bits secured area for unique id ? auto erase and auto program algorithm - automatically erases and verifes data at selected sector - automatically programs and verifes data at selected page by an internal algorithm that automatically times the program pulse widths (any page to be programed should have page in the erased state frst) p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
6 general description the device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. when it is in dual output read mode, the si and so pins become sio0 and sio1 pins for data output. the device provides sequential read operation on whole chip. after program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the speci - fed page or sector/block locations will be executed. program command is executed on byte basis, or page basis, or word basis for erase command is executes on sector, or block, or whole chip basis. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. advanced security features enhance the protection and security functions, please see security features section for more details. when the device is not in operation and cs# is high, it is put in standby mode. the device utilizes macronix's proprietary memory cell, which reliably stores memory contents even after typical 100,000 program and erase cycles. ? status register feature ? electronic identifcation - jedec 1-byte manufacturer id and 2-byte device id - res command for 1-byte device id - rems commands for 1-byte manufacturer id and 1-byte device id hardware features ? package - 8-pin sop (200mil) - all devices are rohs compliant and halogen-free p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
7 pin configurations symbol description cs# chip select si/sio0 serial data input (for 1 x i/o)/ serial data input & output (for dual output mode) so/sio1 serial data output (for 1 x i/o)/ serial data output (for dual output mode) sclk clock input wp# write protection hold# hold, to pause the device without deselecting the device vcc + 3.3v power supply gnd ground pin description 8-pin sop (200mil) 1 2 3 4 cs# so/sio1 wp# gnd vcc hold# sclk si/sio0 8 7 6 5 p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
8 block diagram address generator memory array page buffer y-decoder x-decoder data register sram buffer si/sio0 sclk clock generator state machine mode logic sense amplifier hv generator output buffer so/sio1 cs#, wp#, hold# p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
9 memory organization table 1. memory organization block sector address range 31 511 1ff000h 1fffffh : : : 496 1f0000h 1f0fffh 30 495 1ef000h 1effffh : : : 480 1e0000h 1e0fffh : : : : : : : : 0 15 00f000h 00ffffh : : : 3 003000h 003fffh 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
10 device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended op - eration. 2. when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps the standby mode until next cs# falling edge. in standby mode, so pin of this lsi should be high-z. 3. when correct command is inputted to this lsi, this lsi becomes active mode and keeps the active mode until next cs# rising edge. 4. input data is latched on the rising edge of serial clock(sclk) and data shifts out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown in figure 1. 5. for the following instructions:rdid, rdsr, rdscur, read, fast_read, dread, res, and rems the shift - ed-in instruction sequence is followed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrsr, se, be, ce, pp, rdp, dp, ensa, exsa,and wrscur, the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. during the progress of write status register , program, erase operation, to access the memory array is neglect - ed and not affect the current operation of write status register, program, erase. figure 1. serial modes supported note: cpol indicates clock polarity of serial master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported. sclk msb cpha shift in shift out si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk msb p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
11 data protection during power transition, there may be some false system level signals which result in inadvertent erasure or programming. the device is designed to protect itself from these accidental write cycles. the state machine will be reset as standby mode automatically during power up. in addition, the control register architecture of the device constrains that the memory contents can only be changed after specifc command sequences have completed successfully. in the following, there are several features to protect the system from the accidental write cycles during vcc power- up and power-down or from system noise . ? valid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? write enable (wren) command: wren command is required to set the write enable latch bit (wel) before other command to change data. the wel bit will return to reset stage under following situation: - power-up - write disable (wrdi) command completion - write status register (wrsr) command completion - page program (pp) command completion - sector erase (se) command completion - block erase (be) command completion - chip erase (ce) command completion ? deep power down mode: by entering deep power down mode, the fash device also is under protected from writing all commands except release from deep power down mode command (rdp) and read electronic sig - nature command (res). ? advanced security features: there are some protection and security features which protect content from inad - vertent write and hostile access. i. block lock protection - the software protected mode (spm): mx25l1608e: use (bp3, bp2, bp1, bp0) bits to allow part of memory to be protected as read only. the proect - ed area defnition is shown as table of "protected area sizes", the protected areas are more fexible which may protect various area by setting value of bp0-bp3 bits. please refer to table of "protected area sizes". - the hardware proteced mode (hpm) uses wp# to protect the bp3-bp0 bits and srwd bit. p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
12 table 2. protected area sizes ii. additional 512-bit secured area for unique id: to provide 512-bit read-only unique id data. please refer to table 3. 512-bit secured area defnition. - security register bit 0 indicates whether the chip is locked by factory or not. - to read the 512-bit secured area by entering 512-bit secured area mode (with ensa command), and going through normal read procedure, and then exiting 512-bit secured area mode by writing exsa command. table 3. 512-bit secured area defnition address range size standard factory lock xxxx00~xxxx3f 512-bit unique id status bit protect level bp3 bp2 bp1 bp0 mx25l1608e (16mb) 0 0 0 0 0 (none) 0 0 0 1 1 (1block, block 31th) 0 0 1 0 2 (2blocks, block 30th-31th) 0 0 1 1 3 (4blocks, block 28th-31th) 0 1 0 0 4 (8blocks, block 24th-31th) 0 1 0 1 5 (16blocks, block 16th-31th) 0 1 1 0 6 (32blocks, all) 0 1 1 1 7 (32blocks, all) 1 0 0 0 8 (32blocks, all) 1 0 0 1 9 (32blocks, all) 1 0 1 0 10 (16blocks, block 0th-15th) 1 0 1 1 11 (24blocks, block 0th-23th) 1 1 0 0 12 (28blocks, block 0th-27th) 1 1 0 1 13 (30blocks, block 0th-29th) 1 1 1 0 14 (31blocks, block 0th-30th) 1 1 1 1 15 (32blocks, all) p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
13 hold features hold# pin signal goes low to hold any serial communications with the device. the hold feature will not stop the operation of write status register, programming, or erasing in progress. the operation of hold requires chip select(cs#) keeping low and starts on falling edge of hold# pin signal while serial clock (sclk) signal is being low (if serial clock signal is not being low, hold operation will not start until serial clock signal being low). the hold condition ends on the rising edge of hold# pin signal while se - rial clock(sclk) signal is being low (if serial clock signal is not being low, hold operation will not end until serial clock being low), see figure 2. figure 2. hold condition operation hold# cs# sclk hold condition (standard) hold condition (non-standard) the serial data output (so) is high impedance, both serial data input (si) and serial clock (sclk) are don't care during the hold operation. if chip select (cs#) drives high during hold operation, it will reset the internal logic of the device. to re-start communication with chip, the hold# must be at high and cs# must be at low. p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
14 table 4. command definition command description command (byte) wren (write enable) wrdi (write disable) wrsr (write status register) rdid (read identifc- ation) rdsr (read status register) read (read data) fast read (fast read data) 1st byte 06 (hex) 04 (hex) 01 (hex) 9f (hex) 05 (hex) 03 (hex) 0b (hex) 2nd byte ad1 ad1 3rd byte ad2 ad2 4th byte ad3 ad3 5th byte dummy action sets the (wel) write enable latch bit resets the (wel) write enable latch bit to write new values to the status register outputs jedec id: 1-byte manufact-urer id & 2-byte device id to read out the values of the status register n bytes read out until cs# goes high n bytes read out until cs# goes high command (byte) res (read electronic id) rems (read electronic manufacturer & device id) dread (dual output mode command) se (sector erase) be (block erase) ce (chip erase) pp (page program) 1st byte ab (hex) 90 (hex) 3b (hex) 20 (hex) 52 or d8 (hex) 60 or c7 (hex) 02 (hex) 2nd byte x x ad1 ad1 ad1 ad1 3rd byte x x ad2 ad2 ad2 ad2 4th byte x add (note 1) ad3 ad3 ad3 ad3 5th byte dummy action to read out 1-byte device id output the manufacturer id & device id n bytes read out by dual output until cs# goes high to erase the selected sector to erase the selected block to erase whole chip to program the selected page command (byte) rdscur (read security register) wrscur (write security register) ensa (enter secured area) exsa (exit secured area) dp (deep power down) rdp (release from deep power down) 1st byte 2b (hex) 2f (hex) b1 (hex) c1 (hex) b9 (hex) ab (hex) 2nd byte 3rd byte 4th byte 5th byte action to read value of security register to set the lock-down bit as "1" (once lock-down, cannot be updated) to enter the 512 bits secured area mode to exit the 512 bits secured area mode enters deep power down mode release from deep power down mode note 1: add=00h will output the manufacturer id frst and add=01h will output device id frst. note 2: it is not recommended to adopt any other code not in the command defnition table, which will potentially enter the hidden mode. p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
15 (1) write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, se, be, ce, and wrsr, which are intended to change the device content, should be set every time after the wren in - struction setting the wel bit. the sequence is shown as figure 11 . (2) write disable (wrdi) the write disable (wrdi) instruction is for resetting write enable latch (wel) bit. the sequence is shown as figure 12 . the wel bit is reset by following situations: - power-up - write disable (wrdi) instruction completion - write status register (wrsr) instruction completion - page program (pp) instruction completion - sector erase (se) instruction completion - block erase (be) instruction completion - chip erase (ce) instruction completion (3) read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase/write status register condition) and continuously. it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. the sequence is shown as figure 13 . the defnition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the de - vice will not accept program/erase/write status register instruction. the program/erase command will be ignored and not affect value of wel bit if it is applied to a protected memory area. bp3, bp2, bp1, bp0 bits. the block protect (bp3-bp0) bits, non-volatile bits, indicate the protected area (as de - fned in table 2) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp3-bp0) bits requires the write status register (wrsr) instruction to be executed. those bits defne the protected area of the memory to against pa ge program (pp), sector erase (se), block erase (be) and chip erase (ce) instructions (only if all block protect bits set to 0, the ce instruction can be executed). p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
16 srwd bit. the status register write disable (srwd) bit, non-volatile bit, is operated together with write protection (wp#) pin for providing hardware protection mode. the hardware protection mode requires srwd sets to 1 and wp# pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer accepted for execution and the srwd bit and block protect bits (bp3-bp0) are read only. (4) write status register (wrsr) the wrsr instruction is for changing the values of status register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in ad - vance. the wrsr instruction can change the value of block protect (bp3-bp0) bits to defne the protected area of memory (as shown in table 1). the wrsr also can set or reset the status register write disable (srwd) bit in accordance with write protection (wp#) pin signal. the wrsr instruction cannot be executed once the hardware protected mode (hpm) is entered. the sequence is shown as figure 14 . the wrsr instruction has no effect on b6, b1, b0 of the status register. the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. status register note 1: see the table "protected area size". bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (status register write protect) 0 bp3 (level of protected block) bp2 (level of protected block) bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) 1=status register write disable 0 (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation non-volatile bit 0 non-volatile bit non-volatile bit non-volatile bit non-volatile bit volatile bit volatile bit p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
17 table 5. protection modes note: 1. as defned by the values in the block protect (bp3-bp0) bits of the status register, as shown in table 2. as the above table showing, the summary of the software protected mode (spm) and hardware protected mode (hpm). software protected mode (spm): - when srwd bit=0, no matter wp# is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp3-bp0. the protected area, which is defned by bp3-bp0 is at software protected mode (spm). - when srwd bit=1 and wp# is high, the wren instruction may set the wel bit can change the values of srwd, bp3-bp0. the protected area, which is defned by bp3-bp0 is at software protected mode (spm) note: if srwd bit=1 but wp# is low, it is impossible to write the status register even if the wel bit has previously been set. it is rejected to write the status register and not be executed. hardware protected mode (hpm): - when srwd bit=1, and then wp# is low (or wp# is low before sr wd bit=1), it enters the hardware protected mode (hpm). the data of the protected area is protected by software protected mode by bp3-bp0 and hardware protected mode by the wp# to against data modifcation. note: to exit the hardware protected mode requires wp# driving high once the hardware protected mode is entered. if the wp# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via bp3-bp0. mode status register condition wp# and srwd bit status memory software protection mode (spm) status register can be written in (wel bit is set to "1") and the srwd, bp3-bp0 bits can be changed wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be program or erase. hardware protection mode (hpm) the srwd, bp3-bp0 of status register bits cannot be changed wp#=0, srwd bit=1 the protected area cannot be program or erase. p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
18 (5) read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence is shown as figure 15 . (6) read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence is shown as figure 16 . while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any im - pact on the program/erase/write status register current cycle. (7) dual output mode (dread) the dread instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits(interleave on 1i/2o pins) shift out on the falling edge of sclk at a maxi - mum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single dread instruc - tion. the address counter rolls over to 0 when the highest address has been reached. once writing dread instruc - tion, the data out will perform as 2-bit instead of previous 1-bit. the sequence is shown as figure 17 . while program/erase/write status register cycle is in progress, dread instruction is rejected without any impact on the program/erase/write status register current cycle. the dread only perform read operation. program/erase /read id/read status....operation do not support dread throughputs. (8) sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-byte sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit be - fore sending the sector erase (se). any address of the sector (see table 1) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. address bits [am-a12] (am is the most signifcant address) select the sector address. the sequence is shown as figure 18 . p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
19 the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tse timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3-bp0 bits, the sector erase (se) instruction will not be executed on the page. (9) block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 64k-byte sector erase operation. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the block erase (be). any address of the block (see table 1) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence is shown as figure 19 . the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tbe timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3-bp0 bits, the block erase (be) instruction will not be executed on the page. (10) chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruc - tion must execute to set the write enable latch (wel) bit before sending the chip erase (ce). any address of the sector (see table 1) is a valid address for chip erase (ce) instruction. the cs# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not ex - ecuted. the sequence is shown as figure 20 . the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the chip erase cycle is in progress. the wip sets 1 during the tce timing, and sets 0 when chip erase cycle is completed, and the write enable latch (wel) bit is reset. if the chip is protected by bp3-bp0 bits, the chip erase (ce) instruction will not be executed. it will be only executed when bp3-bp0 all set to "0". (11) page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the page program (pp). the device programs only the last 256 data bytes sent to the device. the last address byte (the 8 least signifcant address bits, a7-a0) should be set to 0 for 256 bytes page program. if a7-a0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. if the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. if the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. there will be no effort on the other data bytes of the same page. the sequence is shown as figure 21 . p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
20 the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the page program cycle is in progress. the wip sets 1 during the tpp timing, and sets 0 when page program cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3-bp0 bits, the page program (pp) instruction will not be executed. (12) deep power-down (dp) the deep power-down (dp) instruction is for setting the device on the minimizing the power consumption (to enter - ing the deep power-down mode, the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to enter during the deep power-down mode, the device is not ac - tive and all write/program/erase instruction are ignored. when cs# goes high, it's only in standby mode not deep power-down mode. it's different from standby mode. the sequence is shown as figure 22 . once the dp instruction is set, all instruction will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction. (those instructions allow the id being reading out). when power- down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for rdp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode and reducing the current to isb2. (13) release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is terminated by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by tres2, and chip se - lect (cs#) must remain high for at least tres2(max), as specifed in table 9. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table of id defnitions. this is not the same as rdid instruction. it is not recommended to use for new design. for new design, please use rdid instruction. even in deep power-down mode, the rdp and res are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/ write cycle in progress. the sequence is shown in figure 23 and figure 24 . the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeat - edly if continuously send the additional clock cycles on sclk while cs# is at low. if the device was not previously in deep power-down mode, the device transition to standby mode is immediate. if the device was previously in deep power-down mode, there's a delay of tres2 to transit to standby mode, and cs# must remain to high at least tres2(max). once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. the rdp instruction is for releasing from deep power down mode. p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
21 (14) read identifcation (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-byte. the mxic manufacturer id and device id are listed as table of "id defnitions". the sequence is shown as figure 25 . while program/erase operation is in progress, it will not decode the rdid instruction, so there's no effect on the cy - cle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby stage. (15) read electronic manufacturer id & device id (rems) the rems instruction is an alternative to the release from power-down/device id instruction that provides both the jedec assigned manufacturer id and the specifc device id. the rems instruction is very similar to the release from power-down/device id instruction. the instruction is initi - ated by driving the cs# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (a7~a0). after which, the manufacturer id for mxic and the device id are shifted out on the falling edge of sclk with most signifcant bit (msb) frst as shown in figure 26 . the device id values are listed in table of id def - nitions. if the one-byte address is initially set to 01h, then the device id will be read frst and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving cs# high. table 6. id definitions (16) enter secured area (ensa) the ensa instruction is for entering the additional 512-bit secured area mode. the additional 512-bit secured area is independent from main array, which is used to store unique id for system identifer. after entering the secured area mode, follow standard read procedure to read out the data. the sequence of issuing ensa instruction is: cs# goes low sending ensa instruction to enter secured area mode cs# goes high. please note that wrsr/wrscur commands are not acceptable during the access of secure area region. (17) exit secured area (exsa) the exsa instruction is for exiting the additional 512-bit secured area mode. the sequence of issuing exsa instruction is: cs# goes low sending exsa instruction to exit secured area mode cs# goes high. command type mx25l1608e rdid command manufacturer id memory type memory density c2 20 15 res command electronic id 14 rems command manufacturer id device id c2 14 p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
22 (18) read security register (rdscur) the rdscur instruction is for reading the value of security register bits. the read security register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. the sequence of issuing rdscur instruction is : cs# goes low send ing rdscur instruction security regis - ter data out on so cs# goes high. the defnition of the security register bits is as below: secured area indicator bit. the secured area indicator bit shows the chip is locked by factory before ex- factory or not. when it is "0", it indicates non- factory lock; "1" indicates factory- lock. table 7. security register definition (19) write security register (wrscur) the wrscur instruction is for changing the values of security register bits. unlike write status register, the wren instruction is not required before sending wrscur instruction. the sequence of issuing wrscur instruction is :cs# goes low sending wrscur instruction cs# goes high. the cs# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 x x x x x x x secured area indicator bit reserved reserved reserved reserved reserved reserved reserved 1 = factory lock (default) volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit non-volatile bit p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
23 power-on state the device is at below states when power-up: - standby mode ( please note it is not deep power-down mode) - write enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage unless the vcc achieves below correct level: - vcc minimum at power-up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. for further protection on the device, if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the read, write, erase, and program command should be sent after the below time delay: - tvsl after vcc reached vcc minimum level the device can accept read command after vcc reached vcc minimum and a time delay of tvsl. please refer to the fgure of "power-up timing". note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommend - ed.(generally around 0.1uf) initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
24 notice: 1. stresses greater than those listed under absolute maximum ra tings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot vss to -2.0v and vcc to +2.0v for periods up to 20ns, see fig - ure 3 and 4. absolute maximum ratings electrical specifications capacitance ta = 25 c, f = 1.0 mhz symbol parameter min. typ max. unit conditions cin input capacitance 6 pf vin = 0v cout output capacitance 8 pf vout = 0v figure 3.maximum negative overshoot waveform figure 4. maximum positive overshoot waveform vss vss-2.0v 20ns 20ns 20ns vcc + 2.0v vcc 20ns 20ns 20ns rating value ambient operating temperature industrial grade -40 c to 85 c storage temperature -65c to 150c applied input voltage -0.5v to 4.6v applied output voltage -0.5v to 4.6v vcc to ground potential -0.5v to 4.6v p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
25 figure 5. input test waveforms and measurement level figure 6. output loading ac measurement level input timing referance level output timing referance level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm +3.3v cl=30pf/15pf including jig capacitance p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
26 table 8. dc characteristics symbol parameter notes min. typ. max. units test conditions ili input load current 1 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max, vin = vcc or gnd isb1 vcc standby current 1 15 25 ua vin = vcc or gnd, cs# = vcc isb2 deep power-down current 2 20 ua vin = vcc or gnd, cs# = vcc icc1 vcc read 1 25 ma f=86mhz ft=80mhz (2 x i/o read) sclk=0.1vcc/0.9vcc, so=open 20 ma f=66mhz, sclk=0.1vcc/0.9vcc, so=open 10 ma f=33mhz, sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 15 20 ma program in progress, cs# = vcc icc3 vcc write status register (wrsr) current 3 20 ma program status register in progress, cs#=vcc icc4 vcc sector erase current (se) 1 9 20 ma erase in progress, cs#=vcc icc5 vcc chip erase current (ce) 1 15 20 ma erase in progress, cs#=vcc vil input low voltage -0.5 0.3vcc v vih input high voltage 0.7vcc vcc+0.4 v vol output low voltage 0.4 v iol = 1.6ma voh output high voltage vcc-0.2 v ioh = -100ua notes : 1. typical values at vcc = 3.3v, t = 25c. these currents are valid for all product versions (package and speeds). 2. not 100% tested. p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
27 table 9. ac characteristics symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for the following instructions: fast_read, pp, se, be, ce, dp, res, rdp, wren, wrdi, rdid, rdsr, wrsr dc 86 mhz frsclk fr clock frequency for read instructions dc 33 mhz ftsclk ft clock frequency for dread instructions dc 80 mhz tch(1) tclh clock high time fc=86mhz 5.5 ns fr=33mhz 13 ns tcl(1) tcll clock low time fc=86mhz 5.5 ns fr=33mhz 13 ns tclch(2) clock rise time (3) (peak to peak) 0.1 v/ns tchcl(2) clock fall time (3) (peak to peak) 0.1 v/ns tslch tcss cs# active setup time (relative to sclk) 5 ns tchsl cs# not active hold time (relative to sclk) 5 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 5 ns tchsh cs# active hold time (relative to sclk) 5 ns tshch cs# not active setup time (relative to sclk) 5 ns tshsl tcsh cs# deselect time read 15 ns write 40 ns tshqz(2) tdis output disable time 6 ns tclqv tv clock low to output valid, loading 30pf/15pf 8 / 6 ns tclqx tho output hold time 0 ns thlch hold# setup time (relative to sclk) 5 ns tchhh hold# hold time (relative to sclk) 5 ns thhch hold setup time (relative to sclk) 5 ns tchhl hold hold time (relative to sclk) 5 ns thhqx(2) tlz hold to output low-z 6 ns thlqz(2) thz hold# to output high-z 6 ns twhsl(4) write protect setup time 20 ns tshwl (4) write protect hold time 100 ns tdp(2) cs# high to deep power-down mode 10 us tres1(2) cs# high to standby mode without electronic signature read 8.8 us tres2(2) cs# high to standby mode with electronic signature read 8.8 us tw write status register cycle time 40 100 ms tbp byte-program 9 50 us tpp page program cycle time 0.6 3 ms tse sector erase cycle time 40 200 ms tbe block erase cycle time 0.4 2 s tce chip erase cycle time 6.5 20 s trpd1 cs# high to power-down 100 ns notes: 1. tch + tcl must be greater than or equal to 1 / f (fc or fr). for fast read, tcl/tch=5.5/5.5. 2. value guaranteed by characterization, not 100% tested in production. 3. expressed as a slew-rate. 4. only applicable as a constraint for a wrsr instruction when srwd is set at 1. 5. test condition is shown as figure 5. p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
28 figure 7. serial input timing sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl figure 8. output timing lsb addr.lsb in tshqz tch tcl tclqx tclqv tclqx tclqv sclk so cs# si timing analysis p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
29 figure 9. hold timing tchhl thlch thhch tchhh thhqx thlqz sclk so cs# hold# * si is "don't care" during hold operation. figure 10. wp# disable setup and hold timing during wrsr when srwd=1 high-z 01 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 twhsl tshwl sclk si cs# wp# so p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
30 figure 11. write enable (wren) sequence (command 06) figure 12. write disable (wrdi) sequence (command 04) 21 34567 high-z 0 06 command sclk si cs# so 21 34567 high-z 0 04 command sclk si cs# so p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
31 figure 13. read status register (rdsr) sequence (command 05) figure 14. write status register (wrsr) sequence (command 01) figure 15. read data bytes (read) sequence (command 03) 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so 05 21 345678 9 10 11 12 13 14 15 status register in 0 76543 2 0 1 msb sclk si cs# so 01 high-z command sclk si cs# so 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 7654 3 1 7 0 data out 1 24-bit address 0 msb msb 2 39 data out 2 03 high-z command p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
32 figure 16. read at higher speed (fast_read) sequence (command 0b) 23 21 345678 9 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 0b command p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
33 figure 17. dual output read mode sequence (command 3b) high impedance 21 345678 0 sclk si/so0 so/so1 cs# 9 10 11 30 31 32 3b(hex) dummy address bit23, bit22, bit21...bit0 data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... 39 40 41 42 43 8 bit instruction 24 bit address 8 dummy cycle data output figure 18. sector erase (se) sequence (command 20) figure 19. block erase (be) sequence (command 52 or d8) note: se command is 20(hex). note: be command is 52 or d8(hex). 24 bit address 21 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si 52 or d8 command 24 bit address 21 3456789 29 30 31 0 23 22 2 1 0 msb sclk cs# si 20 command p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
34 figure 21. page program (pp) sequence (command 02) 4241 43 44 45 46 47 48 49 50 52 53 54 55 40 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 24-bit address 0 76543 2 0 1 data byte 1 39 51 76543 2 0 1 data byte 2 76543 2 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 76543 2 0 1 2072 msb msb msb msb msb sclk cs# si sclk cs# si 02 command figure 20. chip erase (ce) sequence (command 60 or c7) note: ce command is 60(hex) or c7(hex). 21 34567 0 60 or c7 sclk si cs# command p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
35 figure 24. release from deep power-down and read electronic signature (res) sequence (command ab) 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 76543 2 0 1 high-z electronic signature out 3 dummy bytes 0 msb stand-by mode deep power-down mode msb t res2 sclk cs# si so ab command figure 23. release from deep power-down (rdp) sequence (command ab) 21 34567 0 t res1 stand-by mode deep power-down mode high-z sclk cs# si so ab command figure 22. deep power-down (dp) sequence (command b9) 21 34567 0 t dp deep power-down mode stand-by mode sclk cs# si b9 command p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
36 notes: (1) add=00h will output the manufacturer's id frst and add=01h will output device id frst. figure 26. read electronic manufacturer & device id (rems) sequence (command 90) 15 14 13 3 2 1 0 21 345678 9 10 2 dummy bytes 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 manufacturer id add (1) msb 7 6543210 device id msb msb 7 47 76543 2 0 1 35 31302928 sclk si cs# so sclk si cs# so 90 high-z command figure 25. read identifcation (rdid) sequence (command 9f) 21 345678 9 10 11 12 13 14 15 command 0 manufacturer identification high-z msb 15 14 13 3210 device identification msb 7 6 5 3 2 1 0 16 17 18 28 29 30 31 sclk si cs# so 9f p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
37 wr en co mm and program /erase co mm and write progr am data/address (w ri te erase address) rdsr command read array data (same add ress of pgm/ers) program /er ase su ccessfully yes yes program /erase fail no start verify ok? wip=0? progr am /e rase anot her bl ock? prog ram /er ase comp let ed no yes no rds r command yes wel=1? no rdsr command read wel=0 figure 27. program/ erase fow with read array data p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
38 figure 28. power-up timing v cc v cc (min) chip selection is not allowed tvsl time device is fully accessible v cc (max) note: vcc (max.) is 3.6v and vcc (min.) is 2.7v. symbol parameter min. max. unit tvsl(1) vcc(min) to cs# low 200 us note: 1. the parameter is characterized only. table 10. power-up timing p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
39 operating conditions at device power-up and power-down ac timing illustrated in figure 29 and figure 30 are the supply voltages and the control signals at device power-up and power-down. if the timing in the fgures is ignored, the device will not operate correctly . during power-up and power down, cs# need to follow the voltage applied on vcc to keep the device not be se - lected. the cs# can be driven low when vcc reach vcc(min.) and wait a period of tvsl. figure 29. ac timing at device power-up notes : 1. sampled, not 100% tested. 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the fgure, please refer to "ac characteristics" table. symbol parameter notes min. max. unit tvr vcc rise time 1 20 500000 us/v sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
40 figure 30. power-down sequence cs# sclk vcc during power down, cs# need to follow the voltage drop on vcc to avoid mis-operation. p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
41 erase and programming performance min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. latch-up characteristics data retention parameter condition min. max. unit data retention 55?c 20 years note: 1. typical program and erase time assumes the following conditions: 25 c, 3.3v, and checkerboard pattern. 2. under worst conditions of 85 c and 2.7v. 3. system-level overhead is the time required to execute the frst-bus-cycle sequence for the programming com - mand. 4. erase/program cycles comply with jedec: jesd-47 & jesd22-a117 standard. parameter min. typ. (1) max. (2) unit write status register time 40 100 ms sector erase time 40 200 ms block erase time 0.4 2 s chip erase time 6.5 20 s byte program time (via page program command) 9 50 us page program time 0.6 3 ms erase/program cycle 100,000 cycles p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
42 ordering information part no. clock (mhz) operating current max. (ma) standby current max. (ua) temperature package remark mx25l1608em2i-12g 86 25 25 -40 c~85 c 8-sop (200mil) pb-free p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
43 part name description mx 25 l 12 m2 i g option: g: rohs compliant and halogen-free speed: 12: 86mhz temperature range: i: industrial (-40c to 85c) package: m2: 200mil 8-sop density & mode: 1608e: 16mb type: l: 3v device: 25: serial flash 1608e p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
44 package information p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
45 revision history revision no. description page date 1.0 1. initial released all oct/05/2010 1.1 1. updated parameters for dc/ac characteristics p5,26,27 nov/06/2013 2. updated erase and programming performance p5,41 p/n: pm1637 rev. 1.1, nov. 06, 2013 mx25l1608e
46 mx25l1608e macronix international co., ltd. reserves the right to change product and specifcations without notice. except for customized products which has been expressly identifed in the applicable agreement, macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. in the event macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said macronix's product qualifed for its actual use in accordance with the applicable laws and regulations; and macronix as well as its suppliers and/or distributors shall be released from any and all liability arisen therefrom. copyright? macronix international co., ltd. 2010~2013. all rights reserved, including the trademarks and tradename thereof, such as macronix, mxic, mxic logo, mx logo, integrated solutions provider, nbit, nbit, nbiit, macronix nbit, eliteflash, hybridnvm, hybridflash, xtrarom, phines, kh logo, be-sonos, ksmc, kingtech, mxsmio, macronix vee, macronix map, rich au dio, rich book, rich tv, and fitcam. the names and brands of third party referred thereto (if any) are for identifcation purposes only . for the contact and order information, please visit macronixs web site at: http://www.macronix.com

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